1. Field of the Invention
The present invention relates to an apparatus and method for forming a high dielectric constant film and for depositing a metal electrode material film on a high dielectric constant film in manufacturing a metal oxide semiconductor field effect transistor (MOSFET). More specifically, the present invention relates to the apparatus and method for enhancing interfacial properties, in the MOSFET, between the high dielectric constant film and the metal electrode material film while realizing reduction of impurities in the high dielectric constant film and reduction of an equivalent oxide film thickness value. In addition, the present invention relates to a substrate treatment system suitable for this method.
2. Related Background Art
Currently, the metal oxide semiconductor field effect transistor (MOSFET) is manufactured by using a silicon oxide film in a gate insulation film and using polysilicon in a gate electrode and combining them. As a tendency with respect to manufacturing of a semiconductor device, a design rule of the semiconductor device has been reduced gradually for enhancing a performance of an integrated circuit. In connection with this, layer-thinning of the gate insulation film is required. However, in the gate insulation film using the silicon oxide film, the layer-thinning has a limit. That is, the layer-thinning exceeding the limit causes an increase of a leakage current exceeding an allowable range as a result.
Then, an application of the gate insulation film having a relative dielectric constant higher than that of the silicon oxide film is investigated. Such gate insulation film is called a high dielectric constant film. When the high dielectric constant film is used in the gate insulation film, the gate electrode must be changed into a metal electrode from the polysilicon. It is because there are two reasons described in the following. A first one is that polysilicon is not compatible with almost all high dielectric constant films. A second one is that using polysilicon causes the problem that a depletion region is formed in an interface between the polysilicon and the high dielectric constant film, and thereby, an equivalent oxide film thickness (EOT) becomes large and a capacitance is reduced.
Here, described is the equivalent oxide film thickness. An electric film thickness of the insulation film acquired by calculating back from a gate capacitance by assuming, independently of the type of the gate insulation film, that the gate insulation film material is the silicon oxide film, is called a silicon equivalent oxide film thickness (EOT: Equivalent Oxide Thickness). That is, when the relative dielectric constant of the insulation film is Eh, the relative dielectric constant of the silicon oxide film is ∈o, and the thickness of the insulation film is dh, the silicon equivalent oxide film thickness de is expressed by the following formula 1.de=dh*(∈o/∈h)   [Formula 1]
The above formula 1 shows that, when as the gate insulating film, a material is used which has large dielectric constant ∈h in comparison with the relative dielectric constant ∈o of the silicon oxide film, the silicon equivalent oxide film thickness becomes equivalent to the film thickness of the silicon oxide film which is thinner than that of this gate insulation film. The relative dielectric constant ∈o of the silicon oxide film is about 3.9. Accordingly, for example, as for a film comprising a high dielectric constant material of ∈h=39, even though the physical film thickness is 15 nm, the silicon equivalent oxide film thickness (electrical film thickness) becomes to be 1.5 nm, and while a capacitance value of the gate insulation film is kept equivalent to that of the silicon oxide film having the film thickness of 1.5 nm, a tunnel current can be reduced remarkably.
Currently, as a high dielectric constant film formation technology, commonly are used a MO-CVD method, a method for forming the high dielectric constant film by an ALD method, or a method for forming a metal film on the silicon oxide film by using these methods, and for heat-treating it in an atmospheric pressure atmosphere to form the high dielectric constant film. As a metal electrode formation technology, the MO-CVD method or the ALD method is commonly used.
When a stacked structure of the high dielectric constant film and the metal electrode is formed by using above-mentioned methods, there exists a problem that an interface between the high dielectric constant film and the metal electrode is always exposed to the atmosphere, and impurities adhere to the interface between the high dielectric constant film and the metal electrode, thereby giving adverse effect on the electric characteristics. When the CVD method is used, since carbon is included in the raw material, the electric-characteristic degradation due to this impurity also becomes a problem.
In Patent Document 1, as means to enhance the interfacial property between the high dielectric constant film and the metal electrode, after the high dielectric constant film formation, a method for carrying out the transferring to a metal electrode deposition chamber without breaking a vacuum, and for forming the metal electrode is described. However, in Patent Document 1, since any consideration is not paid for oxygen atmosphere control in the heat-treating step during a high dielectric constant film formation process, there arises a problem that the equivalent oxide film thickness value (EOT) becomes thick. Alternatively, there is a problem that a hysteresis is generated in a C-V curve.
Thus, in the formation of the stucked structure of the high dielectric constant film and the metal electrode, it is a subject to realize, at the same time, the reduction of impurities in these film interfaces, the reduction of impurities in the high dielectric constant film, and the reduction of the equivalent oxide film thickness value.
[Patent document 1] Japanese Patent Laid-Open No. 2006-237371